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Senior ASIC Design Engineer (24806)

Cambridge
to £60k DoE + options

Hey there! This is just one of many top career opportunities ECM can suggest — if this job isn't right for you, let us do the hard work! Tell us what you're looking for and we'll start searching for you. We promise to treat your CV as strictly confidential.

ASIC Algorithm implementation

As an ASIC Design Engineer, are you able to deliver high quality, low power, high performance micro-architecture and RTL implementations? In this role you will implement image processing algorithms for photos, however a video background may be of interest to them.

As the Senior ASIC Design Engineer you will have significant design experience backed up by a top engineering degree from a well-known and respected university. You will be able to demonstrate the following:

  • Excellent knowledge of ASIC design flow
  • Ability to create efficient RTL implementations
  • Ensure thorough ASIC Design quality checks are performed on the RTL
  • Good working knowledge of Synopsys/Cadence/Mentor ASIC
  • Creation of efficient image processing algorithms or similar
  • Experience of scripting tools and able to translate C++ algorithms
  • A good understanding of low power design - Power Performance and Area (PPA)

You will join an expanding team of friendly, dedicated developers working in an extremely modern, welcoming work environment. The company plan is focused around technical success creating a leading solution.

There is also a complementary FPGA role should your skills be more in that direction.

Keywords: ASIC, SoC, RTL simulation, System Verilog, Verilog, VHDL, UVM, memory subsystems, AXI, MATLAB, C/C++, scripting, Cambridge, Cambridgeshire.

Please note: even if you don't have exactly the background indicated, do contact us now if this type of job is of interest - we may well have similar opportunities that you would be suited to. And of course, we always get your permission before submitting your CV to a company.