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FPGA/ASIC Verification Engineer (24985)

to £55k DoE

Create the architecture and environment for FPGA and ASIC verification

This is an exciting opportunity to be the key member of a small team where you will have the chance to help build the verification architecture and environment. It is intended that you will create a reusable and scalable verification environment to assist this company in making a high quality synthesizable product.

As the Verification Engineer you will have an engineering degree from a well-known and respected university. During your career so far you will have gained experience in most of the following:

  • Excellent knowledge of UVM methodology
  • Previous experience in the design of System Verilog test strategies
  • Good working knowledge of coverage-driven constrained random test environments
  • Experience of Synopsys, Cadence and Mentor Graphics simulation and coverage tools
  • A good understanding of formal assertions
  • Previous exposure scripting in Python or Perl

You will join an expanding team of friendly, dedicated developers working in an extremely modern and welcoming work environment. The company plan is focused around technical success of their image processing creating a leading edge camera solution.

Keywords: FPGA Verification, ASIC Verification, UVM, System Verilog, Scripting, Image Processing, Cambridge, Cambridgeshire.

Please note: even if you don't have exactly the background indicated, do contact us now if this type of job is of interest - we may well have similar opportunities that you would be suited to. And of course, we always get your permission before submitting your CV to a company.