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Senior ASIC Engineer (26679)

to £65,000 DoE + Benefits

Chip level design for digital (mixed signal) ASICs

Working within a team, the Senior ASIC Engineer will take responsibility for block-level and chip-level design for custom ASICs. This will include from concept to production of the silicon and will involve design specification, architectural development, top-level design and digital / mixed-signal simulation, layout and sign-off. You will work with modern EDA tools, and develop behavioural models of mixed signal designs. You will document all IC designs and associated work.


  • Degree in Electronics Engineering (or similar), and possibly a related PhD.
  • Industry experience working on digital / mixed signal circuit design including SoC architecture, RTL design (VHDL or Verilog), SystemC and MATLAB.
  • Experience with EDA tools for design, verification and implementation of chip-level circuits and simulations.
  • Experience with ARM processors, bus protocols, and processor subsystems.
  • Exposure to touch-screen technologies or piezoelectric devices would be desirable.

On offer is a competitive salary and benefits package. Applications for those who are immediately available or on notice periods will be considered.

Keywords: Digital, Mixed Signal, VHDL / Verilog, Electronics, IC Design, EDA Tools, RTL, Cambridge

Please note: even if you don't have exactly the background indicated, do contact us now if this type of job is of interest - we may well have similar opportunities that you would be suited to. And of course, we always get your permission before submitting your CV to a company.

Recommend for £250 - see www.ecmselection.co.uk/tell-a-friend for details.